1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a high bias device, using a doped well as a drift region of the high-bias semiconductor device.
2. Description of Related Art
As the size of semiconductor device is reduced, the channel length is accordingly reduced resulting in a semiconductor device with a faster operational speed. However, even though the shorter channel length raises the operational speed, a channel length that is too short creates other serious problems. These problems are generally called the short channel effect and are described as follows. If the bias applied on the semiconductor device is kept constant but the channel length is shortened, according to a formula of "electric field (E-field)=bias/channel length", where E-field is measured in units of "V/m", the electrons within the channel gain more energy due to the stronger E-field so that the possibility of an electrical breakdown is higher.
For example, it is quite common for current electronic products, such as a digital versatile disk (DVD) or a liquid crystal display (LCD), to be driven by high bias. A circuit device for driving the DVD and the LCD needs a high bias tolerance of about 12-30 volts. In general, a high-bias semiconductor device mainly utilizes an isolating layer 0 volts. In general, a high-bias semiconductor device mainly utilizes an isolating layer and a drift region under the isolating layer to increase the distance between an interchangeable source/drain and a gate. So, the high-bias semiconductor device can normally work with a high-bias power source.
FIGS. 1A-1D are cross-section views of a high-bias semiconductor device schematically illustrating a conventional fabrication process for a high-bias semiconductor device. In FIG. 1A, a semiconductor substrate doped with a first-type dopant is provided (not shown). Then, a well 10 doped with a second-type dopant is formed on the substrate. If the first-type dopant is N-type then the second-type dopant is P-type, and if the first-type dopant is P-type then the second-type dopant is N-type. The P-type dopant is, for example, boron or gallium, and the N-type dopant is, for example, arsenic or phosphorus. Next, a thermal process is performed on the well 10 to form a pad oxide layer 20 over the well 10. A low chemical vapor deposition (LPCVD) process is performed to form a silicon nitride layer 30 over the pad oxide layer 20.
In FIG. 1A and FIG. 1B, a portion of the silicon nitride layer 30 is removed by photolithography and etching to expose the pad oxide layer 20. The silicon nitride layer 30 becomes a silicon nitride 50, on which a photoresist layer 40 remains. An ion implantation is performed to implant the exposed region of the pad oxide layer 20. A drift region 60 then is formed. The drift region 60 includes, for example, the first type of dopant, gallium.
In FIG. 1C, the photoresist layer 40 is removed. A wet oxidation process is performed by using the silicon nitride layer 50 as a mask to form a field oxide layer 70 above the drift region 60. A bird's beak structure, or an acute structure, occurs on each end of the silicon nitride layer 50. The bird's beak structure is due to a high temperature from the wet oxidation process. The high-temperature environment drives the implanted ions inside the drift region 60 into the well 10 and forms the field oxide layer 70 above the drive region 60, where the field oxide layer 70 is not masked by the silicon nitride layer 50. The field oxide layer 70 pushes each end of the silicon nitride layer 50 to form the bird's beak structure.
In FIG. 1C and FIG. 1D, a wet etching process is performed to remove the silicon nitride layer 50 and the pad oxide layer 20 shown in FIG. 1B so that the well 10 is exposed. Then, a dry oxidation process is performed to form a gate oxide layer 80 over the well 10 and the field oxide layer 70. A gate layer 90 including, for example, polysilicon is formed over the gate oxide layer 80 by, for example, deposition. A portion of the gate oxide layer 80 and the gate layer 90 is removed by photolithography and etching, in which a region of the field oxide layer 70 and the well 10 is exposed. Then an ion implantation process with a high density but low energy condition is performed to implant the first-type dopant into the well 10 on the exposed region. The drift region 60, after implantation, becomes a drift region 100 below the exposed region. A first-type dopant with high density and low energy is doped onto the exposed region of the well 10 on each side of the gate layer 90 to form a source region 110 and a drain region 120.
The conventional high-bias device shown in FIG. 1D needs several photomasks to obtain the desired structure. The high-bias device is separately fabricated in order to serve as an interface to drive other 1C device driven by high bias, such as the DVD or the LCD. In conclusion, this conventional method for fabricating the high-bias device consumes much time and cost for the fabrication of the photomasks. The throughput is also affected.